An important consideration in the design of complementary metal oxide semiconductor (“CMOS”) devices or charge-coupled devices (“CCD”) used for imaging applications, such as digital cameras or camcorders, is the efficient use of power. Limiting the power consumption of such CMOS devices or CCDs can result in increased battery life. Limited power consumption can also aid in the reduced generation of heat, a factor especially important in limiting dark current in imaging devices. Dark current, a type of noise that occurs in light-sensitive detectors, may be lessened by operation at low temperatures.
One significant source of power consumption in an imaging device is the pre-charging of bit-lines. Many imaging devices utilize static random access memory (“SRAM”) arrays to which data may be written or from which data may be read. Data is often written to or read from the arrays in eight- to ten-bit bytes. However, prior to the read/write operation, the bit-lines i.e., the lines on which the bits are posted, are pre-charged, for example, to a high state, thus removing any residual signal on the bit-lines and fully preparing the bit-lines for the read/write operation. The pre-charge transitions require power to charge and discharge the capacitance associated with each bit-line. Because pre-charging is typically done before any read/write operations involving the SRAM, pre-charging occurs frequently, thus resulting in significant power consumption.
Generally, imaging CMOS devices and CCDs have used random access memory (“RAM”) to store the data bytes. However, sequential access memory (“SAM”) devices may also be used. SAM devices function by reading and writing data in a sequential manner—the memory array is linearly searched from a set start point until the desired memory address is found. A major limitation of SAM devices, however, is the fact that data read/write times are dependent on the location of the memory address along the linear search path. An audio tape provides a good example of this limitation. Assuming the tape is at its beginning, one can readily listen to the first part of the tape. However, the tape will need to be fast-forwarded to listen to later portions of the tape. This fast-forward process can become very inefficient, especially if the most accessed memory is not near the start point. On the other hand, read/write operations near the start point can be performed very quickly.
FIG. 1 comprises a block diagram of a conventional SAM device 34. The SAM device 34 is comprised of a memory block 10 and an address block 12. In FIG. 1, the memory block 10 consists of an “m by n” array of memory cells 14, each capable of storing one k-bit word or byte. The address block 12 consists of a row address pointer 16 and a column address pointer 18. The row address pointer 16 and the column address pointer 18 each contain a logic block 20, 21 to direct data through an appropriate registrar 22, 23 to or from the specified memory cell 14 in the memory block 10. A write-data bus 24 carries data to the SAM device 34. Data on the write-data bus 24 is parsed into k-bit words by a de-multiplexer 26 and then directed via a bit-line 28 to the appropriate memory cell 14 by both the row address pointer 16 and the column address pointer 18. Similarly, data leaves the SAM device 34 by traveling on the respective bit-lines 28 through a multiplexer 30 which assimilates the data for transmission on a read-data bus 32.
In contrast to SAM, RAM searches in multiple dimensions for a desired memory address. As a result, the time needed to access data is independent of the data's location on the memory array. For many devices, RAM is preferred over SAM for its increased flexibility and overall faster search times. However, SAM is still used when read/write operations can predictably benefit from the sequential search method.
One example of a class of devices that benefits from the SAM technology is digital signal processing devices. Most notably, digital cameras and camcorders, TV receivers, facsimile devices and copiers all may require the reading and writing of a fixed number of data bytes. Additionally, data bytes may be written and read in a sequential order, thus avoiding the potential limitations of SAM devices.
FIG. 2 illustrates how both SAM and RAM devices conventionally require an initializing pre-charge of the device bit-lines. FIG. 2 shows four related timing diagrams 36, namely diagrams depicting a clock signal 44, a pre-charge signal 46, a read-data signal 48, and a write-data signal 50. As shown, a pre-charge pulse 38 which acts to charge the device bit-lines occurs prior to every read operation 40 or write operation 42. Each pre-charge pulse 38 and subsequent read operation 40 or write operation 42 corresponds with a pulse of the clock signal 44. It should be noted that, although the read-data signal 48 and the write-data signal 50 are both shown on FIG. 2 for comparison purposes, the read-data signal 48 and write-data signal 50 do not necessarily occur at the same time.
The present invention addresses the mitigation of the negative effects of frequent pre-charging in an imaging CMOS or CCD application that utilizes some of the advantages of SAM devices over RAM devices.